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initial incomplete CPU design document #1

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foxpy merged 4 commits from initial-cpu-design into master 2 years ago

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Rirush commented 2 years ago

Owner

I am 100% sure I am missing something important here.
Also of course there is no design for instruction encoding,
so there is a possibility this ISA will not fit into
8-bit instructions.

I am 100% sure I am missing something important here. Also of course there is no design for instruction encoding, so there is a possibility this ISA will not fit into 8-bit instructions.

Rirush added 1 commit 2 years ago

12e489cf19

initial incomplete CPU design document

I am 100% sure I am missing something important here.
Also of course there is no design for instruction encoding,
so there is a possibility this ISA will not fit into
8-bit instructions.

foxpy added 1 commit 2 years ago

b7c479dd8d

draft ISA design specification

I am pretty sure it misses a lot of stuff.
What it definitely misses:
- NOP instruction;
- HALT instructions;
- variable length bit shifts/rotations.

foxpy changed title from initial incomplete CPU design document to WIP: initial incomplete CPU design document 2 years ago

foxpy added 2 commits 2 years ago

43f774762d

finish designing ISA

It looks good for me!

454aa03826

oops: remove near jump

It was interfering with other instructions because it was
using the same instruction encoding.
I have fucked up.

foxpy changed title from WIP: initial incomplete CPU design document to initial incomplete CPU design document 2 years ago

Rirush was assigned by foxpy 2 years ago

foxpy self-assigned this 2 years ago

Rirush requested review from foxpy 2 years ago

Rirush removed review request for foxpy 2 years ago

foxpy commented 2 years ago

Owner

@Rirush plz review

@Rirush plz review

foxpy added this to the Initial release project 2 years ago

foxpy commented 2 years ago

Owner

Looks good enough for me. I don't like the absense of near jumps, but that's my fault. Anyways, in worst case scenario, user needs 1 byte of RAM and 5 instructions to perform a jump: save register to RAM, load jump destination with 2 load immediate instructions, jump, restore register from RAM.

Other than that, I like it and I think we can merge this design and work on it.

Looks good enough for me. I don't like the absense of near jumps, but that's my fault. Anyways, in worst case scenario, user needs 1 byte of RAM and 5 instructions to perform a jump: save register to RAM, load jump destination with 2 load immediate instructions, jump, restore register from RAM. Other than that, I like it and I think we can merge this design and work on it.

foxpy merged commit 1ff6069eff into master 2 years ago

foxpy deleted branch initial-cpu-design 2 years ago

foxpy referenced this issue from a commit 2 years ago

Merge pull request 'initial incomplete CPU design document' (#1) from initial-cpu-design into master

The pull request has been merged as 1ff6069eff.

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