ToyPC
/
ToyCPU-4bit
2
0
Fork 0
Code Issues Pull Requests Projects 1 Releases Wiki Activity
Browse Source

Merge pull request 'initial incomplete CPU design document' (#1) from initial-cpu-design into master 

Reviewed-on: https://git.rfnull.com/ToyPC/ToyCPU-4bit/pulls/1
pull/2/head
foxpy 2 years ago
parent
97920142e1 454aa03826
commit
1ff6069eff
1 changed files with 392 additions and 0 deletions
Whitespace
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
Split View
Diff Options
Show Stats Download Patch File Download Diff File
  1. 392
      DESIGN.md

392
DESIGN.md
View File

@ -0,0 +1,392 @@
# CPU Design
## Memory segments
There are two separate memory segments:
- `CODE` segment is size of 256 bytes and is byte-addressed;
- `DATA` segment is size of 16 bytes and is byte-addressed.
To prevent confusion, we will append segment suffixes to
differentiate between different addresses:
- `0x00_c` — 8-bit address in `CODE` segment;
- `0x0_d` — 4-bit address in `DATA` segment.
## Registers
`IP` — Instruction Pointer, 8-bit register, points to next instruction
in `CODE` segment. Cannot be directly accessed. Is automatically advanced
after execution of every instruction.
`R0` — First register of ALU. Always used as destination and
as first operand for all ALU operations.
`R1` — Second register of ALU. Always used as second operand for all
ALU operations.
`C` — 1-bit carry flag.
## ISA
### LOAD/STORE
```
+—+—+—+—+———————+
|0|0|M|R|A A A A|
+—+—+—+—+———————+
```
`M` — `0` for load (read byte from memory and put in ALU register),
`1` for store (read byte from ALU register and put in memory).
`R` — `0` to use `R0` register, `1` to use `R1` register.
`AAAA` — 4-bit address in `DATA` segment.
### LOAD IMMEDIATE
```
+—+—+—+—+———————+
|0|1|H|R|I I I I|
+—+—+—+—+———————+
```
`H` — `0` to use 4 least significant bits, `1` to use 4 most
significant bits.
`R` — `0` to use `R0` register, `1` to use `R1` register.
`IIII` — 4-bit immediate value.
### FAR JUMP
```
+—+—+—+—+—+—+—+—+
|1|0|0|0|0|0|R|C|
+—+—+—+—+—+—+—+—+
```
Jumps at `CODE` segment address.
`R` — `0` to use address stored in `R0` register, `1` to use address
stored in `R1` register.
`C` — `0` to ignore carry flag and jump unconditionally,
`1` to only jump if carry flag is set.
### COMPARISON
#### equal
```
+—+—+—+—+—+—+—+—+
|1|0|0|0|0|1|0|0|
+—+—+—+—+—+—+—+—+
```
Write `1` to `C` if value in `R0` equals value in `R1`,
write `0` otherwise.
#### greater
```
+—+—+—+—+—+—+—+—+
|1|0|0|0|0|1|0|1|
+—+—+—+—+—+—+—+—+
```
Write `1` to `C` if value in `R0` is greater than value in `R1`,
write `0` otherwise.
#### less
```
+—+—+—+—+—+—+—+—+
|1|0|0|0|0|1|1|0|
+—+—+—+—+—+—+—+—+
```
Write `1` to `C` if value in `R0` is less than value in `R1`,
write `0` otherwise.
#### not
```
+—+—+—+—+—+—+—+—+
|1|0|0|0|0|1|1|1|
+—+—+—+—+—+—+—+—+
```
Flips value in `C`. Use it to implement 'not equal', 'greater or equal',
and 'less or equal' comparisons.
### BIT SHIFT RIGHT
```
+—+—+—+—+—+—————+
|1|0|1|R|M|L L L|
+—+—+—+—+—+—————+
```
`R` — `0` to shift bits in `R0` register, `1` in `R1` register.
`M` — mode of operation, `0` — logical shift, `1` — circular shift.
`L` — length of shift.
### BIT SHIFT LEFT
```
+—+—+—+—+—+—————+
|1|1|0|R|M|L L L|
+—+—+—+—+—+—————+
```
`R` — `0` to shift bits in `R0` register, `1` in `R1` register.
`M` — mode of operation, `0` — logical shift, `1` — circular shift.
`L` — length of shift.
### INCREMENT
```
+—+—+—+—+—+—+—+—+
|1|1|1|0|0|0|0|R|
+—+—+—+—+—+—+—+—+
```
Increments ALU register and sets `C` if result is zero.
`R` — `0` to increment `R0` and `1` to increment `R1`.
### DECREMENT
```
+—+—+—+—+—+—+—+—+
|1|1|1|0|0|0|1|R|
+—+—+—+—+—+—+—+—+
```
Decrements ALU register and sets `C` if result is zero.
`R` — `0` to decrement `R0` and `1` to decrement `R1`.
### ADD
```
+—+—+—+—+—+—+—+—+
|1|1|1|0|0|1|0|0|
+—+—+—+—+—+—+—+—+
```
Adds values from `R0` and `R1` and stores result in `R0`.
Sets `C` if result overflows.
### SUBTRACT
```
+—+—+—+—+—+—+—+—+
|1|1|1|0|0|1|0|1|
+—+—+—+—+—+—+—+—+
```
Subtracts `R1` from `R0` and stores result in `R0`.
Sets `C` if result underflows.
### AND
```
+—+—+—+—+—+—+—+—+
|1|1|1|0|0|1|1|0|
+—+—+—+—+—+—+—+—+
```
Bitwise AND operation using values from `R0` and `R1`
and storing result in `R0`.
### OR
```
+—+—+—+—+—+—+—+—+
|1|1|1|0|0|1|1|1|
+—+—+—+—+—+—+—+—+
```
Bitwise OR operation using values from `R0` and `R1`
and storing result in `R0`.
### XOR
```
+—+—+—+—+—+—+—+—+
|1|1|1|0|1|0|0|0|
+—+—+—+—+—+—+—+—+
```
Bitwise XOR operation using values from `R0` and `R1`
and storing result in `R0`.
### XNOR
```
+—+—+—+—+—+—+—+—+
|1|1|1|0|1|0|0|1|
+—+—+—+—+—+—+—+—+
```
Bitwise XNOR operation using values from `R0` and `R1`
and storing result in `R0`.
### ONE'S COMPLEMENT
```
+—+—+—+—+—+—+—+—+
|1|1|1|0|1|0|1|R|
+—+—+—+—+—+—+—+—+
```
Flip all bits in ALU register.
`R` — `0` to use `R0`, `1` to use `R1`.
### VARIABLE BIT SHIFT
```
+—+—+—+—+—+—+—+—+
|1|1|1|0|1|1|D|M|
+—+—+—+—+—+—+—+—+
```
Shifts value in `R0` by length specified in `R1` and stores result in `R0`.
If `R1` value is greater than 8, `R0` is zeroed.
`C` is set if `R0` is zeroed.
`D` — direction: `0` to shift bits right, `1` — left.
`M` — mode of operation, `0` — logical shift, `1` — circular shift.
### COPY
```
+—+—+—+—+—+—+—+—+
|1|1|1|1|0|0|0|R|
+—+—+—+—+—+—+—+—+
```
`R` — `0` to copy data from `R0` to `R1`, `1` to copy data from `R1` to `R0`.
### SETC
```
+—+—+—+—+—+—+—+—+
|1|1|1|1|0|0|1|C|
+—+—+—+—+—+—+—+—+
```
`C` — value copied to `C` flag.
### NOP
```
+—+—+—+—+—+—+—+—+
|1|1|1|1|0|1|0|0|
+—+—+—+—+—+—+—+—+
```
### RESET
```
+—+—+—+—+—+—+—+—+
|1|1|1|1|0|1|0|1|
+—+—+—+—+—+—+—+—+
```
Resets CPU registers and memory and zeroes `IP`.
### CLOAD
```
+—+—+—+—+—+—+—+—+
|1|1|1|1|0|1|1|R|
+—+—+—+—+—+—+—+—+
```
Loads byte from `CODE` segment at address specified in `R0`
and puts it into ALU register.
`R` — `0` to store result in `R0`, `1` to store result in `R1`.
### ZERO
```
+—+—+—+—+—+—+—+—+
|1|1|1|1|1|0|0|R|
+—+—+—+—+—+—+—+—+
```
`R` — `0` to zero out `R0`, `1` to zero out `R1`.
### DIV
```
+—+—+—+—+—+—+—+—+
|1|1|1|1|1|0|1|0|
+—+—+—+—+—+—+—+—+
```
Divides `R0` by `R1`. Stores quotient in `R0` and remainder in `R1`.
If `R1` is 0 before division, sets `R0` to all ones and `R1` to all zeroes,
also sets `C` flag.
### MUL
```
+—+—+—+—+—+—+—+—+
|1|1|1|1|1|0|1|1|
+—+—+—+—+—+—+—+—+
```
Multiplies `R0` by `R1`. Result is unsigned 16-bit value. Most significant
byte is stored in `R0` and least significant byte is stored in `R1`.
### SWAP
```
+—+—+—+—+—+—+—+—+
|1|1|1|1|1|1|0|0|
+—+—+—+—+—+—+—+—+
```
Swaps values of `R0` and `R1`.
### PORT READY
```
+—+—+—+—+—+—+—+—+
|1|1|1|1|1|1|0|1|
+—+—+—+—+—+—+—+—+
```
If there is data available to read from port, sets `C` flag.
Otherwise, unsets `C` flag.
### READ PORT
```
+—+—+—+—+—+—+—+—+
|1|1|1|1|1|1|1|0|
+—+—+—+—+—+—+—+—+
```
Reads byte from port and stores result in `R0`. If there is no
data available from port, zeroes out `R0`.
### WRITE PORT
```
+—+—+—+—+—+—+—+—+
|1|1|1|1|1|1|1|1|
+—+—+—+—+—+—+—+—+
```
Writes byte from `R0` to port.
Write Preview
Loading…
Cancel
Save