initial incomplete CPU design document

I am 100% sure I am missing something important here.
Also of course there is no design for instruction encoding,
so there is a possibility this ISA will not fit into
8-bit instructions.

DESIGN.md

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+# CPU Design
+
+## Memory segments
+
+There are two separate memory segments:
+- `CODE` segment is size of 256 bytes and is byte-addressed;
+- `DATA` segment is size of 16 bytes and is byte-addressed.
+
+There is also a bit-addressed subset in `DATA` segment.
+
+To prevent confusion, we will append segment suffixes to
+differentiate between different addresses:
+- `0x00_c` — 8-bit address in `CODE` segment;
+- `0x0_d` — 4-bit address in `DATA` segment;
+- `0x0_b` — 4-bit address in bit-addressed subset of `DATA` segment.
+
+Last 2 bytes of `DATA` segment are bit-addressed, with:
+- `0x0_b` address pointing to least significant bit in byte at `0xE_d`;
+- `0x7_b` address pointing to most significant bit in byte at `0xE_d`;
+- `0x8_b` address pointing to least significant bit in byte at `0xF_d`;
+- `0xF_b` address pointing to most significant bit in byte at `0xF_d`.
+
+## Registers
+
+`IP` — Instruction Pointer, 8-bit register, points to current instruction
+in `CODE` segment. Cannot be directly accessed. Is automatically advanced
+after execution of every instruction.
+
+`R0` — First register of ALU. Always used as destination and
+as first operand for all ALU operations.
+
+`R1` — Second register of ALU. Always used as second operand for all
+ALU operations.
+
+`C` — 1-bit carry flag.
+
+`O` — 1-bit overflow flag.
+
+`R` — 1-bit result of comparison instruction.