draft ISA design specification

I am pretty sure it misses a lot of stuff.
What it definitely misses:
- NOP instruction;
- HALT instructions;
- variable length bit shifts/rotations.

DESIGN.md

@@ -6,23 +6,14 @@ There are two separate memory segments:
 - `CODE` segment is size of 256 bytes and is byte-addressed;
 - `DATA` segment is size of 16 bytes and is byte-addressed.
 
-There is also a bit-addressed subset in `DATA` segment.
-
 To prevent confusion, we will append segment suffixes to
 differentiate between different addresses:
 - `0x00_c` — 8-bit address in `CODE` segment;
-- `0x0_d` — 4-bit address in `DATA` segment;
-- `0x0_b` — 4-bit address in bit-addressed subset of `DATA` segment.
-
-Last 2 bytes of `DATA` segment are bit-addressed, with:
-- `0x0_b` address pointing to least significant bit in byte at `0xE_d`;
-- `0x7_b` address pointing to most significant bit in byte at `0xE_d`;
-- `0x8_b` address pointing to least significant bit in byte at `0xF_d`;
-- `0xF_b` address pointing to most significant bit in byte at `0xF_d`.
+- `0x0_d` — 4-bit address in `DATA` segment.
 
 ## Registers
 
-`IP` — Instruction Pointer, 8-bit register, points to current instruction
+`IP` — Instruction Pointer, 8-bit register, points to next instruction
 in `CODE` segment. Cannot be directly accessed. Is automatically advanced
 after execution of every instruction.
 
@@ -34,6 +25,225 @@ ALU operations.
 
 `C` — 1-bit carry flag.
 
-`O` — 1-bit overflow flag.
+## ISA
+
+### LOAD/STORE
+
+```
++—+—+—+—+———————+
+|0|0|M|R|A A A A|
++—+—+—+—+———————+
+```
+
+`M` — `0` for load (read byte from memory and put in ALU register),
+`1` for store (read byte from ALU register and put in memory).
+
+`R` — `0` to use `R0` register, `1` to use `R1` register.
+
+`AAAA` — 4-bit address in `DATA` segment.
+
+### LOAD IMMEDIATE
+
+```
++—+—+—+—+———————+
+|0|1|H|R|I I I I|
++—+—+—+—+———————+
+```
+
+`H` — `0` to use 4 least significant bits, `1` to use 4 most
+significant bits.
+
+`R` — `0` to use `R0` register, `1` to use `R1` register.
+
+`IIII` — 4-bit immediate value.
+
+### NEAR JUMP
+
+```
++—+—+—+—+———————+
+|1|0|C|D|O O O O|
++—+—+—+—+———————+
+```
+
+`C` — `0` to ignore carry flag and jump unconditionally,
+`1` to only jump if carry flag is set.
+
+`D` — direction of jump, `1` to jump forward, `0` to jump backward.
+
+`OOOO` — jump offset.
+
+### FAR JUMP
+
+```
++—+—+—+—+—+—+—+—+
+|1|0|0|0|0|0|R|C|
++—+—+—+—+—+—+—+—+
+```
+
+Jumps at `CODE` segment address.
+
+`R` — `0` to use address stored in `R0` register, `1` to use address
+stored in `R1` register.
+
+`C` — `0` to ignore carry flag and jump unconditionally,
+`1` to only jump if carry flag is set.
+
+### COMPARISON
+
+#### equal
+
+```
++—+—+—+—+—+—+—+—+
+|1|0|0|0|0|1|0|0|
++—+—+—+—+—+—+—+—+
+```
+
+Write `1` to `C` if value in `R0` equals value in `R1`,
+write `0` otherwise.
+
+#### greater
+
+```
++—+—+—+—+—+—+—+—+
+|1|0|0|0|0|1|0|1|
++—+—+—+—+—+—+—+—+
+```
+
+Write `1` to `C` if value in `R0` is greater than value in `R1`,
+write `0` otherwise.
+
+#### less
+
+```
++—+—+—+—+—+—+—+—+
+|1|0|0|0|0|1|1|0|
++—+—+—+—+—+—+—+—+
+```
+
+Write `1` to `C` if value in `R0` is less than value in `R1`,
+write `0` otherwise.
+
+#### not
+
+```
++—+—+—+—+—+—+—+—+
+|1|0|0|0|0|1|1|1|
++—+—+—+—+—+—+—+—+
+```
+
+Flips value in `C`. Use it to implement 'not equal', 'greater or equal',
+and 'less or equal' comparisons.
+
+### BIT SHIFT
+
+```
++—+—+—+—+—+—————+
+|1|0|1|R|M|L L L|
++—+—+—+—+—+—————+
+```
+
+`R` — `0` to shift bits in `R0` register, `1` in `R1` register.
+
+`M` — mode of operation, `0` — logical shift, `1` — circular shift.
+
+### INCREMENT
+
+```
++—+—+—+—+—+—+—+—+
+|1|1|0|0|0|0|0|R|
++—+—+—+—+—+—+—+—+
+```
+
+Increments ALU register and sets `C` if result is zero.
+
+`R` — `0` to increment `R0` and `1` to increment `R1`.
+
+### DECREMENT
+
+```
++—+—+—+—+—+—+—+—+
+|1|1|0|0|0|0|1|R|
++—+—+—+—+—+—+—+—+
+```
+
+Decrements ALU register and sets `C` if result is zero.
+
+`R` — `0` to decrement `R0` and `1` to decrement `R1`.
+
+### ADD
+
+```
++—+—+—+—+—+—+—+—+
+|1|1|0|0|0|1|0|0|
++—+—+—+—+—+—+—+—+
+```
+
+Adds values from `R0` and `R1` and stores result in `R0`.
+Sets `C` if result overflows.
+
+### SUBTRACT
+
+```
++—+—+—+—+—+—+—+—+
+|1|1|0|0|0|1|0|1|
++—+—+—+—+—+—+—+—+
+```
+
+Subtracts `R1` from `R0` and stores result in `R0`.
+Sets `C` if result underflows.
+
+### AND
+
+```
++—+—+—+—+—+—+—+—+
+|1|1|0|0|0|1|1|0|
++—+—+—+—+—+—+—+—+
+```
+
+Bitwise AND operation using values from `R0` and `R1`
+and storing result in `R0`.
+
+### OR
+
+```
++—+—+—+—+—+—+—+—+
+|1|1|0|0|0|1|1|1|
++—+—+—+—+—+—+—+—+
+```
+
+Bitwise OR operation using values from `R0` and `R1`
+and storing result in `R0`.
+
+### XOR
+
+```
++—+—+—+—+—+—+—+—+
+|1|1|0|0|1|0|0|0|
++—+—+—+—+—+—+—+—+
+```
+
+Bitwise XOR operation using values from `R0` and `R1`
+and storing result in `R0`.
+
+### XNOR
+
+```
++—+—+—+—+—+—+—+—+
+|1|1|0|0|1|0|0|1|
++—+—+—+—+—+—+—+—+
+```
+
+Bitwise XNOR operation using values from `R0` and `R1`
+and storing result in `R0`.
+
+### ONE'S COMPLEMENT
+
+```
++—+—+—+—+—+—+—+—+
+|1|1|0|0|1|0|1|R|
++—+—+—+—+—+—+—+—+
+```
+
+Flip all bits in ALU register.
 
-`R` — 1-bit result of comparison instruction.
+`R` — `0` to use `R0`, `1` to use `R1`.