foxpy
2 years ago
1 changed files with 392 additions and 0 deletions
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# CPU Design |
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## Memory segments |
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There are two separate memory segments: |
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- `CODE` segment is size of 256 bytes and is byte-addressed; |
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- `DATA` segment is size of 16 bytes and is byte-addressed. |
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To prevent confusion, we will append segment suffixes to |
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differentiate between different addresses: |
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- `0x00_c` — 8-bit address in `CODE` segment; |
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- `0x0_d` — 4-bit address in `DATA` segment. |
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## Registers |
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`IP` — Instruction Pointer, 8-bit register, points to next instruction |
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in `CODE` segment. Cannot be directly accessed. Is automatically advanced |
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after execution of every instruction. |
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`R0` — First register of ALU. Always used as destination and |
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as first operand for all ALU operations. |
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`R1` — Second register of ALU. Always used as second operand for all |
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ALU operations. |
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`C` — 1-bit carry flag. |
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## ISA |
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### LOAD/STORE |
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``` |
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+—+—+—+—+———————+ |
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|0|0|M|R|A A A A| |
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+—+—+—+—+———————+ |
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``` |
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`M` — `0` for load (read byte from memory and put in ALU register), |
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`1` for store (read byte from ALU register and put in memory). |
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`R` — `0` to use `R0` register, `1` to use `R1` register. |
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`AAAA` — 4-bit address in `DATA` segment. |
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### LOAD IMMEDIATE |
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``` |
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+—+—+—+—+———————+ |
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|0|1|H|R|I I I I| |
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+—+—+—+—+———————+ |
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``` |
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`H` — `0` to use 4 least significant bits, `1` to use 4 most |
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significant bits. |
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`R` — `0` to use `R0` register, `1` to use `R1` register. |
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`IIII` — 4-bit immediate value. |
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### FAR JUMP |
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``` |
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+—+—+—+—+—+—+—+—+ |
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|1|0|0|0|0|0|R|C| |
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+—+—+—+—+—+—+—+—+ |
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``` |
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Jumps at `CODE` segment address. |
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`R` — `0` to use address stored in `R0` register, `1` to use address |
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stored in `R1` register. |
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`C` — `0` to ignore carry flag and jump unconditionally, |
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`1` to only jump if carry flag is set. |
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### COMPARISON |
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#### equal |
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``` |
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+—+—+—+—+—+—+—+—+ |
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|1|0|0|0|0|1|0|0| |
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+—+—+—+—+—+—+—+—+ |
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``` |
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Write `1` to `C` if value in `R0` equals value in `R1`, |
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write `0` otherwise. |
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#### greater |
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``` |
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+—+—+—+—+—+—+—+—+ |
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|1|0|0|0|0|1|0|1| |
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+—+—+—+—+—+—+—+—+ |
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``` |
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Write `1` to `C` if value in `R0` is greater than value in `R1`, |
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write `0` otherwise. |
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#### less |
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``` |
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+—+—+—+—+—+—+—+—+ |
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|1|0|0|0|0|1|1|0| |
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+—+—+—+—+—+—+—+—+ |
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``` |
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Write `1` to `C` if value in `R0` is less than value in `R1`, |
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write `0` otherwise. |
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#### not |
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``` |
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+—+—+—+—+—+—+—+—+ |
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|1|0|0|0|0|1|1|1| |
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+—+—+—+—+—+—+—+—+ |
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``` |
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Flips value in `C`. Use it to implement 'not equal', 'greater or equal', |
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and 'less or equal' comparisons. |
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### BIT SHIFT RIGHT |
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``` |
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+—+—+—+—+—+—————+ |
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|1|0|1|R|M|L L L| |
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+—+—+—+—+—+—————+ |
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``` |
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`R` — `0` to shift bits in `R0` register, `1` in `R1` register. |
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`M` — mode of operation, `0` — logical shift, `1` — circular shift. |
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`L` — length of shift. |
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### BIT SHIFT LEFT |
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``` |
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+—+—+—+—+—+—————+ |
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|1|1|0|R|M|L L L| |
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+—+—+—+—+—+—————+ |
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``` |
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`R` — `0` to shift bits in `R0` register, `1` in `R1` register. |
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`M` — mode of operation, `0` — logical shift, `1` — circular shift. |
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`L` — length of shift. |
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### INCREMENT |
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``` |
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+—+—+—+—+—+—+—+—+ |
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|1|1|1|0|0|0|0|R| |
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+—+—+—+—+—+—+—+—+ |
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``` |
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Increments ALU register and sets `C` if result is zero. |
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`R` — `0` to increment `R0` and `1` to increment `R1`. |
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### DECREMENT |
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``` |
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+—+—+—+—+—+—+—+—+ |
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|1|1|1|0|0|0|1|R| |
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+—+—+—+—+—+—+—+—+ |
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``` |
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Decrements ALU register and sets `C` if result is zero. |
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`R` — `0` to decrement `R0` and `1` to decrement `R1`. |
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### ADD |
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``` |
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+—+—+—+—+—+—+—+—+ |
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|1|1|1|0|0|1|0|0| |
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+—+—+—+—+—+—+—+—+ |
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``` |
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Adds values from `R0` and `R1` and stores result in `R0`. |
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Sets `C` if result overflows. |
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### SUBTRACT |
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``` |
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+—+—+—+—+—+—+—+—+ |
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|1|1|1|0|0|1|0|1| |
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+—+—+—+—+—+—+—+—+ |
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``` |
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Subtracts `R1` from `R0` and stores result in `R0`. |
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Sets `C` if result underflows. |
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### AND |
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``` |
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+—+—+—+—+—+—+—+—+ |
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|1|1|1|0|0|1|1|0| |
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+—+—+—+—+—+—+—+—+ |
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``` |
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Bitwise AND operation using values from `R0` and `R1` |
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and storing result in `R0`. |
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### OR |
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``` |
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+—+—+—+—+—+—+—+—+ |
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|1|1|1|0|0|1|1|1| |
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+—+—+—+—+—+—+—+—+ |
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``` |
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Bitwise OR operation using values from `R0` and `R1` |
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and storing result in `R0`. |
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### XOR |
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``` |
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+—+—+—+—+—+—+—+—+ |
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|1|1|1|0|1|0|0|0| |
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+—+—+—+—+—+—+—+—+ |
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``` |
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Bitwise XOR operation using values from `R0` and `R1` |
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and storing result in `R0`. |
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### XNOR |
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``` |
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+—+—+—+—+—+—+—+—+ |
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|1|1|1|0|1|0|0|1| |
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+—+—+—+—+—+—+—+—+ |
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``` |
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Bitwise XNOR operation using values from `R0` and `R1` |
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and storing result in `R0`. |
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### ONE'S COMPLEMENT |
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``` |
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+—+—+—+—+—+—+—+—+ |
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|1|1|1|0|1|0|1|R| |
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+—+—+—+—+—+—+—+—+ |
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``` |
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Flip all bits in ALU register. |
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`R` — `0` to use `R0`, `1` to use `R1`. |
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### VARIABLE BIT SHIFT |
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``` |
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+—+—+—+—+—+—+—+—+ |
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|1|1|1|0|1|1|D|M| |
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+—+—+—+—+—+—+—+—+ |
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``` |
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Shifts value in `R0` by length specified in `R1` and stores result in `R0`. |
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If `R1` value is greater than 8, `R0` is zeroed. |
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`C` is set if `R0` is zeroed. |
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`D` — direction: `0` to shift bits right, `1` — left. |
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`M` — mode of operation, `0` — logical shift, `1` — circular shift. |
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### COPY |
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``` |
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+—+—+—+—+—+—+—+—+ |
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|1|1|1|1|0|0|0|R| |
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+—+—+—+—+—+—+—+—+ |
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``` |
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`R` — `0` to copy data from `R0` to `R1`, `1` to copy data from `R1` to `R0`. |
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### SETC |
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``` |
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+—+—+—+—+—+—+—+—+ |
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|1|1|1|1|0|0|1|C| |
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+—+—+—+—+—+—+—+—+ |
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``` |
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`C` — value copied to `C` flag. |
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### NOP |
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``` |
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+—+—+—+—+—+—+—+—+ |
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|1|1|1|1|0|1|0|0| |
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+—+—+—+—+—+—+—+—+ |
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``` |
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### RESET |
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``` |
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+—+—+—+—+—+—+—+—+ |
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|1|1|1|1|0|1|0|1| |
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+—+—+—+—+—+—+—+—+ |
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``` |
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Resets CPU registers and memory and zeroes `IP`. |
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### CLOAD |
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``` |
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+—+—+—+—+—+—+—+—+ |
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|1|1|1|1|0|1|1|R| |
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+—+—+—+—+—+—+—+—+ |
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``` |
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Loads byte from `CODE` segment at address specified in `R0` |
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and puts it into ALU register. |
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`R` — `0` to store result in `R0`, `1` to store result in `R1`. |
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### ZERO |
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``` |
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+—+—+—+—+—+—+—+—+ |
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|1|1|1|1|1|0|0|R| |
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+—+—+—+—+—+—+—+—+ |
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``` |
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`R` — `0` to zero out `R0`, `1` to zero out `R1`. |
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### DIV |
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``` |
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+—+—+—+—+—+—+—+—+ |
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|1|1|1|1|1|0|1|0| |
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+—+—+—+—+—+—+—+—+ |
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``` |
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Divides `R0` by `R1`. Stores quotient in `R0` and remainder in `R1`. |
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If `R1` is 0 before division, sets `R0` to all ones and `R1` to all zeroes, |
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also sets `C` flag. |
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### MUL |
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``` |
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+—+—+—+—+—+—+—+—+ |
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|1|1|1|1|1|0|1|1| |
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+—+—+—+—+—+—+—+—+ |
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``` |
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Multiplies `R0` by `R1`. Result is unsigned 16-bit value. Most significant |
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byte is stored in `R0` and least significant byte is stored in `R1`. |
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### SWAP |
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``` |
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+—+—+—+—+—+—+—+—+ |
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|1|1|1|1|1|1|0|0| |
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+—+—+—+—+—+—+—+—+ |
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``` |
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Swaps values of `R0` and `R1`. |
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### PORT READY |
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``` |
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+—+—+—+—+—+—+—+—+ |
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|1|1|1|1|1|1|0|1| |
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+—+—+—+—+—+—+—+—+ |
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``` |
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If there is data available to read from port, sets `C` flag. |
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Otherwise, unsets `C` flag. |
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### READ PORT |
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``` |
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+—+—+—+—+—+—+—+—+ |
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|1|1|1|1|1|1|1|0| |
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+—+—+—+—+—+—+—+—+ |
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``` |
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Reads byte from port and stores result in `R0`. If there is no |
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data available from port, zeroes out `R0`. |
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### WRITE PORT |
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``` |
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+—+—+—+—+—+—+—+—+ |
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|1|1|1|1|1|1|1|1| |
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+—+—+—+—+—+—+—+—+ |
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``` |
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Writes byte from `R0` to port. |
Loading…
Reference in new issue