From 12e489cf196f51c32d7736a76ddb897e8354ee3c Mon Sep 17 00:00:00 2001
From: Murad <muradkarammaev@gmail.com>
Date: Tue, 25 Jan 2022 21:55:44 +0300
Subject: [PATCH 1/4] initial incomplete CPU design document

I am 100% sure I am missing something important here.
Also of course there is no design for instruction encoding,
so there is a possibility this ISA will not fit into
8-bit instructions.
---
 DESIGN.md | 39 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 39 insertions(+)
 create mode 100644 DESIGN.md

diff --git a/DESIGN.md b/DESIGN.md
new file mode 100644
index 0000000..fc31a3e
--- /dev/null
+++ b/DESIGN.md
@@ -0,0 +1,39 @@
+# CPU Design
+
+## Memory segments
+
+There are two separate memory segments:
+- `CODE` segment is size of 256 bytes and is byte-addressed;
+- `DATA` segment is size of 16 bytes and is byte-addressed.
+
+There is also a bit-addressed subset in `DATA` segment.
+
+To prevent confusion, we will append segment suffixes to
+differentiate between different addresses:
+- `0x00_c` — 8-bit address in `CODE` segment;
+- `0x0_d` — 4-bit address in `DATA` segment;
+- `0x0_b` — 4-bit address in bit-addressed subset of `DATA` segment.
+
+Last 2 bytes of `DATA` segment are bit-addressed, with:
+- `0x0_b` address pointing to least significant bit in byte at `0xE_d`;
+- `0x7_b` address pointing to most significant bit in byte at `0xE_d`;
+- `0x8_b` address pointing to least significant bit in byte at `0xF_d`;
+- `0xF_b` address pointing to most significant bit in byte at `0xF_d`.
+
+## Registers
+
+`IP` — Instruction Pointer, 8-bit register, points to current instruction
+in `CODE` segment. Cannot be directly accessed. Is automatically advanced
+after execution of every instruction.
+
+`R0` — First register of ALU. Always used as destination and
+as first operand for all ALU operations.
+
+`R1` — Second register of ALU. Always used as second operand for all
+ALU operations.
+
+`C` — 1-bit carry flag.
+
+`O` — 1-bit overflow flag.
+
+`R` — 1-bit result of comparison instruction.

From b7c479dd8d8911b662a3cbafddb54e758b3169b7 Mon Sep 17 00:00:00 2001
From: Murad <muradkarammaev@gmail.com>
Date: Wed, 26 Jan 2022 13:39:53 +0300
Subject: [PATCH 2/4] draft ISA design specification

I am pretty sure it misses a lot of stuff.
What it definitely misses:
- NOP instruction;
- HALT instructions;
- variable length bit shifts/rotations.
---
 DESIGN.md | 236 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++----
 1 file changed, 223 insertions(+), 13 deletions(-)

diff --git a/DESIGN.md b/DESIGN.md
index fc31a3e..ee8b775 100644
--- a/DESIGN.md
+++ b/DESIGN.md
@@ -6,23 +6,14 @@ There are two separate memory segments:
 - `CODE` segment is size of 256 bytes and is byte-addressed;
 - `DATA` segment is size of 16 bytes and is byte-addressed.
 
-There is also a bit-addressed subset in `DATA` segment.
-
 To prevent confusion, we will append segment suffixes to
 differentiate between different addresses:
 - `0x00_c` — 8-bit address in `CODE` segment;
-- `0x0_d` — 4-bit address in `DATA` segment;
-- `0x0_b` — 4-bit address in bit-addressed subset of `DATA` segment.
-
-Last 2 bytes of `DATA` segment are bit-addressed, with:
-- `0x0_b` address pointing to least significant bit in byte at `0xE_d`;
-- `0x7_b` address pointing to most significant bit in byte at `0xE_d`;
-- `0x8_b` address pointing to least significant bit in byte at `0xF_d`;
-- `0xF_b` address pointing to most significant bit in byte at `0xF_d`.
+- `0x0_d` — 4-bit address in `DATA` segment.
 
 ## Registers
 
-`IP` — Instruction Pointer, 8-bit register, points to current instruction
+`IP` — Instruction Pointer, 8-bit register, points to next instruction
 in `CODE` segment. Cannot be directly accessed. Is automatically advanced
 after execution of every instruction.
 
@@ -34,6 +25,225 @@ ALU operations.
 
 `C` — 1-bit carry flag.
 
-`O` — 1-bit overflow flag.
+## ISA
+
+### LOAD/STORE
+
+```
++—+—+—+—+———————+
+|0|0|M|R|A A A A|
++—+—+—+—+———————+
+```
+
+`M` — `0` for load (read byte from memory and put in ALU register),
+`1` for store (read byte from ALU register and put in memory).
+
+`R` — `0` to use `R0` register, `1` to use `R1` register.
+
+`AAAA` — 4-bit address in `DATA` segment.
+
+### LOAD IMMEDIATE
+
+```
++—+—+—+—+———————+
+|0|1|H|R|I I I I|
++—+—+—+—+———————+
+```
+
+`H` — `0` to use 4 least significant bits, `1` to use 4 most
+significant bits.
+
+`R` — `0` to use `R0` register, `1` to use `R1` register.
+
+`IIII` — 4-bit immediate value.
+
+### NEAR JUMP
+
+```
++—+—+—+—+———————+
+|1|0|C|D|O O O O|
++—+—+—+—+———————+
+```
+
+`C` — `0` to ignore carry flag and jump unconditionally,
+`1` to only jump if carry flag is set.
+
+`D` — direction of jump, `1` to jump forward, `0` to jump backward.
+
+`OOOO` — jump offset.
+
+### FAR JUMP
+
+```
++—+—+—+—+—+—+—+—+
+|1|0|0|0|0|0|R|C|
++—+—+—+—+—+—+—+—+
+```
+
+Jumps at `CODE` segment address.
+
+`R` — `0` to use address stored in `R0` register, `1` to use address
+stored in `R1` register.
+
+`C` — `0` to ignore carry flag and jump unconditionally,
+`1` to only jump if carry flag is set.
+
+### COMPARISON
+
+#### equal
+
+```
++—+—+—+—+—+—+—+—+
+|1|0|0|0|0|1|0|0|
++—+—+—+—+—+—+—+—+
+```
+
+Write `1` to `C` if value in `R0` equals value in `R1`,
+write `0` otherwise.
+
+#### greater
+
+```
++—+—+—+—+—+—+—+—+
+|1|0|0|0|0|1|0|1|
++—+—+—+—+—+—+—+—+
+```
+
+Write `1` to `C` if value in `R0` is greater than value in `R1`,
+write `0` otherwise.
+
+#### less
+
+```
++—+—+—+—+—+—+—+—+
+|1|0|0|0|0|1|1|0|
++—+—+—+—+—+—+—+—+
+```
+
+Write `1` to `C` if value in `R0` is less than value in `R1`,
+write `0` otherwise.
+
+#### not
+
+```
++—+—+—+—+—+—+—+—+
+|1|0|0|0|0|1|1|1|
++—+—+—+—+—+—+—+—+
+```
+
+Flips value in `C`. Use it to implement 'not equal', 'greater or equal',
+and 'less or equal' comparisons.
+
+### BIT SHIFT
+
+```
++—+—+—+—+—+—————+
+|1|0|1|R|M|L L L|
++—+—+—+—+—+—————+
+```
+
+`R` — `0` to shift bits in `R0` register, `1` in `R1` register.
+
+`M` — mode of operation, `0` — logical shift, `1` — circular shift.
+
+### INCREMENT
+
+```
++—+—+—+—+—+—+—+—+
+|1|1|0|0|0|0|0|R|
++—+—+—+—+—+—+—+—+
+```
+
+Increments ALU register and sets `C` if result is zero.
+
+`R` — `0` to increment `R0` and `1` to increment `R1`.
+
+### DECREMENT
+
+```
++—+—+—+—+—+—+—+—+
+|1|1|0|0|0|0|1|R|
++—+—+—+—+—+—+—+—+
+```
+
+Decrements ALU register and sets `C` if result is zero.
+
+`R` — `0` to decrement `R0` and `1` to decrement `R1`.
+
+### ADD
+
+```
++—+—+—+—+—+—+—+—+
+|1|1|0|0|0|1|0|0|
++—+—+—+—+—+—+—+—+
+```
+
+Adds values from `R0` and `R1` and stores result in `R0`.
+Sets `C` if result overflows.
+
+### SUBTRACT
+
+```
++—+—+—+—+—+—+—+—+
+|1|1|0|0|0|1|0|1|
++—+—+—+—+—+—+—+—+
+```
+
+Subtracts `R1` from `R0` and stores result in `R0`.
+Sets `C` if result underflows.
+
+### AND
+
+```
++—+—+—+—+—+—+—+—+
+|1|1|0|0|0|1|1|0|
++—+—+—+—+—+—+—+—+
+```
+
+Bitwise AND operation using values from `R0` and `R1`
+and storing result in `R0`.
+
+### OR
+
+```
++—+—+—+—+—+—+—+—+
+|1|1|0|0|0|1|1|1|
++—+—+—+—+—+—+—+—+
+```
+
+Bitwise OR operation using values from `R0` and `R1`
+and storing result in `R0`.
+
+### XOR
+
+```
++—+—+—+—+—+—+—+—+
+|1|1|0|0|1|0|0|0|
++—+—+—+—+—+—+—+—+
+```
+
+Bitwise XOR operation using values from `R0` and `R1`
+and storing result in `R0`.
+
+### XNOR
+
+```
++—+—+—+—+—+—+—+—+
+|1|1|0|0|1|0|0|1|
++—+—+—+—+—+—+—+—+
+```
+
+Bitwise XNOR operation using values from `R0` and `R1`
+and storing result in `R0`.
+
+### ONE'S COMPLEMENT
+
+```
++—+—+—+—+—+—+—+—+
+|1|1|0|0|1|0|1|R|
++—+—+—+—+—+—+—+—+
+```
+
+Flip all bits in ALU register.
 
-`R` — 1-bit result of comparison instruction.
+`R` — `0` to use `R0`, `1` to use `R1`.

From 43f774762dd3fd2b79ef3605fb02a289f6c82f2c Mon Sep 17 00:00:00 2001
From: Murad <muradkarammaev@gmail.com>
Date: Wed, 26 Jan 2022 20:24:50 +0300
Subject: [PATCH 3/4] finish designing ISA

It looks good for me!
---
 DESIGN.md | 178 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++----
 1 file changed, 168 insertions(+), 10 deletions(-)

diff --git a/DESIGN.md b/DESIGN.md
index ee8b775..d7cd0d8 100644
--- a/DESIGN.md
+++ b/DESIGN.md
@@ -134,7 +134,7 @@ write `0` otherwise.
 Flips value in `C`. Use it to implement 'not equal', 'greater or equal',
 and 'less or equal' comparisons.
 
-### BIT SHIFT
+### BIT SHIFT RIGHT
 
 ```
 +—+—+—+—+—+—————+
@@ -146,11 +146,27 @@ and 'less or equal' comparisons.
 
 `M` — mode of operation, `0` — logical shift, `1` — circular shift.
 
+`L` — length of shift.
+
+### BIT SHIFT LEFT
+
+```
++—+—+—+—+—+—————+
+|1|1|0|R|M|L L L|
++—+—+—+—+—+—————+
+```
+
+`R` — `0` to shift bits in `R0` register, `1` in `R1` register.
+
+`M` — mode of operation, `0` — logical shift, `1` — circular shift.
+
+`L` — length of shift.
+
 ### INCREMENT
 
 ```
 +—+—+—+—+—+—+—+—+
-|1|1|0|0|0|0|0|R|
+|1|1|1|0|0|0|0|R|
 +—+—+—+—+—+—+—+—+
 ```
 
@@ -162,7 +178,7 @@ Increments ALU register and sets `C` if result is zero.
 
 ```
 +—+—+—+—+—+—+—+—+
-|1|1|0|0|0|0|1|R|
+|1|1|1|0|0|0|1|R|
 +—+—+—+—+—+—+—+—+
 ```
 
@@ -174,7 +190,7 @@ Decrements ALU register and sets `C` if result is zero.
 
 ```
 +—+—+—+—+—+—+—+—+
-|1|1|0|0|0|1|0|0|
+|1|1|1|0|0|1|0|0|
 +—+—+—+—+—+—+—+—+
 ```
 
@@ -185,7 +201,7 @@ Sets `C` if result overflows.
 
 ```
 +—+—+—+—+—+—+—+—+
-|1|1|0|0|0|1|0|1|
+|1|1|1|0|0|1|0|1|
 +—+—+—+—+—+—+—+—+
 ```
 
@@ -196,7 +212,7 @@ Sets `C` if result underflows.
 
 ```
 +—+—+—+—+—+—+—+—+
-|1|1|0|0|0|1|1|0|
+|1|1|1|0|0|1|1|0|
 +—+—+—+—+—+—+—+—+
 ```
 
@@ -207,7 +223,7 @@ and storing result in `R0`.
 
 ```
 +—+—+—+—+—+—+—+—+
-|1|1|0|0|0|1|1|1|
+|1|1|1|0|0|1|1|1|
 +—+—+—+—+—+—+—+—+
 ```
 
@@ -218,7 +234,7 @@ and storing result in `R0`.
 
 ```
 +—+—+—+—+—+—+—+—+
-|1|1|0|0|1|0|0|0|
+|1|1|1|0|1|0|0|0|
 +—+—+—+—+—+—+—+—+
 ```
 
@@ -229,7 +245,7 @@ and storing result in `R0`.
 
 ```
 +—+—+—+—+—+—+—+—+
-|1|1|0|0|1|0|0|1|
+|1|1|1|0|1|0|0|1|
 +—+—+—+—+—+—+—+—+
 ```
 
@@ -240,10 +256,152 @@ and storing result in `R0`.
 
 ```
 +—+—+—+—+—+—+—+—+
-|1|1|0|0|1|0|1|R|
+|1|1|1|0|1|0|1|R|
 +—+—+—+—+—+—+—+—+
 ```
 
 Flip all bits in ALU register.
 
 `R` — `0` to use `R0`, `1` to use `R1`.
+
+### VARIABLE BIT SHIFT
+
+```
++—+—+—+—+—+—+—+—+
+|1|1|1|0|1|1|D|M|
++—+—+—+—+—+—+—+—+
+```
+
+Shifts value in `R0` by length specified in `R1` and stores result in `R0`.
+If `R1` value is greater than 8, `R0` is zeroed.
+`C` is set if `R0` is zeroed.
+
+`D` — direction: `0` to shift bits right, `1` — left.
+
+`M` — mode of operation, `0` — logical shift, `1` — circular shift.
+
+### COPY
+
+```
++—+—+—+—+—+—+—+—+
+|1|1|1|1|0|0|0|R|
++—+—+—+—+—+—+—+—+
+```
+
+`R` — `0` to copy data from `R0` to `R1`, `1` to copy data from `R1` to `R0`.
+
+### SETC
+
+```
++—+—+—+—+—+—+—+—+
+|1|1|1|1|0|0|1|C|
++—+—+—+—+—+—+—+—+
+```
+
+`C` — value copied to `C` flag.
+
+### NOP
+
+```
++—+—+—+—+—+—+—+—+
+|1|1|1|1|0|1|0|0|
++—+—+—+—+—+—+—+—+
+```
+
+### HALT
+
+```
++—+—+—+—+—+—+—+—+
+|1|1|1|1|0|1|0|1|
++—+—+—+—+—+—+—+—+
+```
+
+Resets CPU registers and memory and zeroes `IP`.
+
+### CLOAD
+
+```
++—+—+—+—+—+—+—+—+
+|1|1|1|1|0|1|1|R|
++—+—+—+—+—+—+—+—+
+```
+
+Loads byte from `CODE` segment at address specified in `R0`
+and puts it into ALU register.
+
+`R` — `0` to store result in `R0`, `1` to store result in `R1`.
+
+### ZERO
+
+```
++—+—+—+—+—+—+—+—+
+|1|1|1|1|1|0|0|R|
++—+—+—+—+—+—+—+—+
+```
+
+`R` — `0` to zero out `R0`, `1` to zero out `R1`.
+
+### DIV
+
+```
++—+—+—+—+—+—+—+—+
+|1|1|1|1|1|0|1|0|
++—+—+—+—+—+—+—+—+
+```
+
+Divides `R0` by `R1`. Stores quotient in `R0` and remainder in `R1`.
+If `R1` is 0 before division, sets `R0` to all ones and `R1` to all zeroes,
+also sets `C` flag.
+
+### MUL
+
+```
++—+—+—+—+—+—+—+—+
+|1|1|1|1|1|0|1|1|
++—+—+—+—+—+—+—+—+
+```
+
+Multiplies `R0` by `R1`. Result is unsigned 16-bit value. Most significant
+byte is stored in `R0` and least significant byte is stored in `R1`.
+
+### SWAP
+
+```
++—+—+—+—+—+—+—+—+
+|1|1|1|1|1|1|0|0|
++—+—+—+—+—+—+—+—+
+```
+
+Swaps values of `R0` and `R1`.
+
+### PORT READY
+
+```
++—+—+—+—+—+—+—+—+
+|1|1|1|1|1|1|0|1|
++—+—+—+—+—+—+—+—+
+```
+
+If there is data available to read from port, sets `C` flag.
+Otherwise, unsets `C` flag.
+
+### READ PORT
+
+```
++—+—+—+—+—+—+—+—+
+|1|1|1|1|1|1|1|0|
++—+—+—+—+—+—+—+—+
+```
+
+Reads byte from port and stores result in `R0`. If there is no
+data available from port, zeroes out `R0`.
+
+### WRITE PORT
+
+```
++—+—+—+—+—+—+—+—+
+|1|1|1|1|1|1|1|1|
++—+—+—+—+—+—+—+—+
+```
+
+Writes byte from `R0` to port.

From 454aa038265d15cbf54da5c21330569481ca5188 Mon Sep 17 00:00:00 2001
From: Murad <muradkarammaev@gmail.com>
Date: Wed, 26 Jan 2022 20:28:38 +0300
Subject: [PATCH 4/4] oops: remove near jump

It was interfering with other instructions because it was
using the same instruction encoding.
I have fucked up.
---
 DESIGN.md | 17 +----------------
 1 file changed, 1 insertion(+), 16 deletions(-)

diff --git a/DESIGN.md b/DESIGN.md
index d7cd0d8..3064f67 100644
--- a/DESIGN.md
+++ b/DESIGN.md
@@ -57,21 +57,6 @@ significant bits.
 
 `IIII` — 4-bit immediate value.
 
-### NEAR JUMP
-
-```
-+—+—+—+—+———————+
-|1|0|C|D|O O O O|
-+—+—+—+—+———————+
-```
-
-`C` — `0` to ignore carry flag and jump unconditionally,
-`1` to only jump if carry flag is set.
-
-`D` — direction of jump, `1` to jump forward, `0` to jump backward.
-
-`OOOO` — jump offset.
-
 ### FAR JUMP
 
 ```
@@ -308,7 +293,7 @@ If `R1` value is greater than 8, `R0` is zeroed.
 +—+—+—+—+—+—+—+—+
 ```
 
-### HALT
+### RESET
 
 ```
 +—+—+—+—+—+—+—+—+