Browse Source

Merge pull request 'Add basic CPU visualization function' (#4) from basic-visualization into master

Reviewed-on: https://git.rfnull.com/ToyPC/ToyCPU-4bit/pulls/4
pull/5/head
foxpy 2 years ago
parent
commit
bd6241398f
  1. 29
      src/cpu.rs
  2. 10
      src/main.rs

29
src/cpu.rs

@ -18,6 +18,7 @@ pub struct Cpu {
data: [u8; 0x10],
port_in: VecDeque<u8>,
port_out: VecDeque<u8>,
num_cycles: u64,
}
impl Cpu {
@ -34,6 +35,7 @@ impl Cpu {
data: [0u8; 0x10],
port_in: VecDeque::<u8>::new(),
port_out: VecDeque::<u8>::new(),
num_cycles: 0,
}
}
@ -329,6 +331,7 @@ impl Cpu {
}
pub fn step(&mut self) -> bool {
self.num_cycles += 1;
let insn = decode(self.code[self.IP.0 as usize]);
match insn {
Instruction::Load { reg, addr } => self.load(reg, addr),
@ -376,6 +379,32 @@ impl Cpu {
}
false
}
pub fn visualize(&self) {
println!("+--+----+----------+");
println!("|IP|{:#04X}|{:#010b}|", self.IP, self.IP);
println!("|R0|{:#04X}|{:#010b}|", self.R0, self.R0);
println!("|R1|{:#04X}|{:#010b}|", self.R1, self.R1);
println!("+--+----+----------+");
println!("|FLAGS:{} |", if self.C { "C" } else { " " });
println!("+------------------+");
println!("|CYCLES:{:11}|", self.num_cycles);
println!("|PORTIN:{:11}|", self.port_in.len());
println!("|PORTOUT:{:10}|", self.port_out.len());
println!("+------------------+");
println!("| MEM +0|+1|+2|+3 |");
for i in 0..4 {
println!(
"| 0x{:X} {:02X}|{:02X}|{:02X}|{:02X} |",
i * 4,
self.data[i * 4 + 0],
self.data[i * 4 + 1],
self.data[i * 4 + 2],
self.data[i * 4 + 3]
);
}
println!("+------------------+");
}
}
#[cfg(test)]

10
src/main.rs

@ -7,10 +7,18 @@ mod instruction;
use cpu::*;
fn main() {
let mut cpu = Cpu::new(&[]);
let mut cpu = Cpu::new(&[
0b01001111, // R0 = 0xF
0b01010011, // R1.l = 0x3
0b11100100, // ADD
0b00100000, // [0] = R0
0b11111000, // R0 = 0
0b11110101, // HALT
]);
loop {
if cpu.step() {
break;
}
}
cpu.visualize();
}

Loading…
Cancel
Save