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@ -18,6 +18,7 @@ pub struct Cpu { |
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data: [u8; 0x10], |
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port_in: VecDeque<u8>, |
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port_out: VecDeque<u8>, |
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num_cycles: u64, |
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} |
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impl Cpu { |
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@ -34,6 +35,7 @@ impl Cpu { |
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data: [0u8; 0x10], |
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port_in: VecDeque::<u8>::new(), |
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port_out: VecDeque::<u8>::new(), |
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num_cycles: 0, |
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} |
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} |
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@ -329,6 +331,7 @@ impl Cpu { |
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} |
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pub fn step(&mut self) -> bool { |
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self.num_cycles += 1; |
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let insn = decode(self.code[self.IP.0 as usize]); |
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match insn { |
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Instruction::Load { reg, addr } => self.load(reg, addr), |
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@ -376,6 +379,32 @@ impl Cpu { |
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} |
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false |
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} |
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pub fn visualize(&self) { |
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println!("+--+----+----------+"); |
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println!("|IP|{:#04X}|{:#010b}|", self.IP, self.IP); |
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println!("|R0|{:#04X}|{:#010b}|", self.R0, self.R0); |
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println!("|R1|{:#04X}|{:#010b}|", self.R1, self.R1); |
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println!("+--+----+----------+"); |
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println!("|FLAGS:{} |", if self.C { "C" } else { " " }); |
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println!("+------------------+"); |
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println!("|CYCLES:{:11}|", self.num_cycles); |
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println!("|PORTIN:{:11}|", self.port_in.len()); |
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println!("|PORTOUT:{:10}|", self.port_out.len()); |
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println!("+------------------+"); |
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println!("| MEM +0|+1|+2|+3 |"); |
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for i in 0..4 { |
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println!( |
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"| 0x{:X} {:02X}|{:02X}|{:02X}|{:02X} |", |
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i * 4, |
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self.data[i * 4 + 0], |
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self.data[i * 4 + 1], |
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self.data[i * 4 + 2], |
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self.data[i * 4 + 3] |
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); |
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} |
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println!("+------------------+"); |
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} |
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} |
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#[cfg(test)] |
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