@ -18,6 +18,7 @@ pub struct Cpu {
data : [ u8 ; 0x10 ] ,
port_in : VecDeque < u8 > ,
port_out : VecDeque < u8 > ,
num_cycles : u64 ,
}
impl Cpu {
@ -34,6 +35,7 @@ impl Cpu {
data : [ 0 u8 ; 0x10 ] ,
port_in : VecDeque ::< u8 > ::new ( ) ,
port_out : VecDeque ::< u8 > ::new ( ) ,
num_cycles : 0 ,
}
}
@ -329,6 +331,7 @@ impl Cpu {
}
pub fn step ( & mut self ) -> bool {
self . num_cycles + = 1 ;
let insn = decode ( self . code [ self . IP . 0 as usize ] ) ;
match insn {
Instruction ::Load { reg , addr } = > self . load ( reg , addr ) ,
@ -376,6 +379,32 @@ impl Cpu {
}
false
}
pub fn visualize ( & self ) {
println ! ( "+--+----+----------+" ) ;
println ! ( "|IP|{:#04X}|{:#010b}|" , self . IP , self . IP ) ;
println ! ( "|R0|{:#04X}|{:#010b}|" , self . R0 , self . R0 ) ;
println ! ( "|R1|{:#04X}|{:#010b}|" , self . R1 , self . R1 ) ;
println ! ( "+--+----+----------+" ) ;
println ! ( "|FLAGS:{} |" , if self . C { "C" } else { " " } ) ;
println ! ( "+------------------+" ) ;
println ! ( "|CYCLES:{:11}|" , self . num_cycles ) ;
println ! ( "|PORTIN:{:11}|" , self . port_in . len ( ) ) ;
println ! ( "|PORTOUT:{:10}|" , self . port_out . len ( ) ) ;
println ! ( "+------------------+" ) ;
println ! ( "| MEM +0|+1|+2|+3 |" ) ;
for i in 0 . . 4 {
println ! (
"| 0x{:X} {:02X}|{:02X}|{:02X}|{:02X} |" ,
i * 4 ,
self . data [ i * 4 + 0 ] ,
self . data [ i * 4 + 1 ] ,
self . data [ i * 4 + 2 ] ,
self . data [ i * 4 + 3 ]
) ;
}
println ! ( "+------------------+" ) ;
}
}
#[ cfg(test) ]