add integration test

src/cpu.rs

@@ -7,15 +7,15 @@ use ux::{u3, u4};
 
 #[allow(non_snake_case)]
 pub struct Cpu {
-    IP: Wrapping<u8>,
-    R0: Wrapping<u8>,
-    R1: Wrapping<u8>,
-    C: bool,
-    code: [u8; 0x100],
-    data: [u8; 0x10],
-    port_in: VecDeque<u8>,
-    port_out: VecDeque<u8>,
-    num_cycles: u64,
+    pub IP: Wrapping<u8>,
+    pub R0: Wrapping<u8>,
+    pub R1: Wrapping<u8>,
+    pub C: bool,
+    pub code: [u8; 0x100],
+    pub data: [u8; 0x10],
+    pub port_in: VecDeque<u8>,
+    pub port_out: VecDeque<u8>,
+    pub num_cycles: u64,
 }
 
 impl Cpu {

src/lib.rs

@@ -4,3 +4,35 @@
 pub mod assembler;
 pub mod cpu;
 pub mod instruction;
+
+#[cfg(test)]
+mod tests {
+    use crate::{assembler::Assembler, cpu::Cpu};
+    use std::num::Wrapping;
+
+    #[test]
+    fn integration_assemble_execute() {
+        let code = r#"
+            MOV R0.l, 0xF  # R0 = 15
+            MOV R1.l, 0x3  # R1 = 3
+            ADD            # R0 += R1 (18)
+            MOV [0], R0    # MEM[0] = R0 (18)
+            ZERO R0        # R0 = 0
+            HALT           # EXIT
+        "#;
+        let code = Assembler::new().assemble(code).unwrap();
+        let mut cpu = Cpu::new(&code);
+        for _ in 0..5 {
+            assert!(!cpu.step()); // CPU does not halt…
+        }
+        assert!(cpu.step()); // …until it reaches halt instruction
+        assert_eq!(cpu.IP, Wrapping(5)); // IP points at halt instruction
+        assert_eq!(cpu.R0, Wrapping(0));
+        assert_eq!(cpu.R1, Wrapping(3));
+        assert!(!cpu.C);
+        assert_eq!(cpu.data[0], 18);
+        for i in 1..=15 {
+            assert_eq!(cpu.data[i], 0);
+        }
+    }
+}