8 changed files with 925 additions and 19 deletions
@ -1 +1,2 @@ |
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target/ |
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.idea/ |
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@ -0,0 +1,717 @@ |
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// SPDX-License-Identifier: MIT
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// Copyright Murad Karammaev, Nikita Kuzmin
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use crate::instruction::{decode, encode, Instruction, Register, ShiftMode}; |
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use regex::Regex; |
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use std::error::Error; |
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use ux::{u2, u3, u4}; |
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type InstructionDecoder = fn(&str, &Regex) -> Result<Instruction, Box<dyn Error>>; |
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const REGEX_REG: &str = r"(R[01])"; |
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const REGEX_REG_HALF: &str = r"(R[01]\.[lh])"; |
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const REGEX_NUM: &str = r"(\d{1,3}|0b[01]{1,8}|0o[0-7]{1,3}|0x[\da-fA-F]{1,2})"; |
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const REGEX_INUM: &str = r"(-?\d{1,3}|-?0b[01]{1,8}|-?0o[0-7]{1,3}|-?0x[\da-fA-F]{1,2})"; |
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const REGEX_ADDR: &str = r"\[(\d{1,3}|0b[01]{1,8}|0o[0-7]{1,3}|0x[\da-fA-F]{1,2})\]"; |
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const REGEX_COMMA: &str = r"\s*,\s*"; |
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const REGEX_CARRY: &str = r"([01])"; |
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macro_rules! asm_entry { |
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($regex:expr, $handler:expr) => { |
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(Regex::new(&$regex).unwrap(), $handler) |
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}; |
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} |
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pub struct Assembler { |
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table: Vec<(Regex, InstructionDecoder)>, |
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} |
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impl Assembler { |
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pub fn new() -> Self { |
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Assembler { |
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table: vec![ |
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asm_entry!(format!(r"^BYTE\s{}$", REGEX_NUM), parse_byte), |
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asm_entry!( |
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format!(r"^MOV\s{}{}{}$", REGEX_REG, REGEX_COMMA, REGEX_ADDR), |
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parse_mov_reg_mem |
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), |
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asm_entry!( |
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format!(r"^MOV\s{}{}{}$", REGEX_ADDR, REGEX_COMMA, REGEX_REG), |
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parse_mov_mem_reg |
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), |
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asm_entry!( |
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format!(r"^MOV\s{}{}{}$", REGEX_REG_HALF, REGEX_COMMA, REGEX_NUM), |
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parse_mov_reg_half_imm |
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), |
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asm_entry!( |
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format!(r"^MOV\s{}{}{}", REGEX_REG, REGEX_COMMA, REGEX_REG), |
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parse_mov_reg_reg |
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), |
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asm_entry!(format!(r"^JMP\s{}$", REGEX_INUM), parse_jmp), |
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asm_entry!(format!(r"^JMPC\s{}$", REGEX_INUM), parse_jmpc), |
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asm_entry!(format!(r"^AJMP\s{}$", REGEX_REG), parse_ajmp), |
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asm_entry!(format!(r"^AJMPC\s{}$", REGEX_REG), parse_ajmpc), |
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asm_entry!(r"^EQ$", |_, _| Ok(Instruction::CmpEqual)), |
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asm_entry!(r"^GT$", |_, _| Ok(Instruction::CmpGreater)), |
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asm_entry!(r"^LE$", |_, _| Ok(Instruction::CmpLess)), |
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asm_entry!(r"^NOT$", |_, _| Ok(Instruction::Not)), |
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asm_entry!(r"^SHR$", |_, _| Ok(Instruction::BitShiftVar { |
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mode: ShiftMode::Logical, |
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right: true |
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})), |
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asm_entry!(r"^SHL$", |_, _| Ok(Instruction::BitShiftVar { |
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mode: ShiftMode::Logical, |
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right: false |
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})), |
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asm_entry!(r"^ROTR$", |_, _| Ok(Instruction::BitShiftVar { |
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mode: ShiftMode::Circular, |
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right: true |
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})), |
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asm_entry!(r"^ROTL$", |_, _| Ok(Instruction::BitShiftVar { |
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mode: ShiftMode::Circular, |
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right: false |
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})), |
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asm_entry!( |
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format!(r"^SHR\s{}{}{}$", REGEX_REG, REGEX_COMMA, REGEX_NUM), |
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parse_shr |
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), |
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asm_entry!( |
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format!(r"^SHL\s{}{}{}$", REGEX_REG, REGEX_COMMA, REGEX_NUM), |
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parse_shl |
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), |
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asm_entry!( |
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format!(r"^ROTR\s{}{}{}$", REGEX_REG, REGEX_COMMA, REGEX_NUM), |
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parse_rotr |
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), |
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asm_entry!( |
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format!(r"^ROTL\s{}{}{}$", REGEX_REG, REGEX_COMMA, REGEX_NUM), |
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parse_rotl |
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), |
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asm_entry!(format!(r"^INC\s{}$", REGEX_REG), parse_inc), |
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asm_entry!(format!(r"^DEC\s{}$", REGEX_REG), parse_dec), |
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asm_entry!(r"^ADD$", |_, _| Ok(Instruction::Add)), |
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asm_entry!(r"^SUB$", |_, _| Ok(Instruction::Sub)), |
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asm_entry!(r"^AND$", |_, _| Ok(Instruction::And)), |
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asm_entry!(r"^OR$", |_, _| Ok(Instruction::Or)), |
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asm_entry!(r"^XOR$", |_, _| Ok(Instruction::Xor)), |
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asm_entry!(r"^XNOR$", |_, _| Ok(Instruction::Xnor)), |
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asm_entry!(format!(r"^COMPL\s{}$", REGEX_REG), parse_compl), |
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asm_entry!(format!(r"^SETC\s{}$", REGEX_CARRY), parse_setc), |
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asm_entry!(r"^NOP$", |_, _| Ok(Instruction::Nop)), |
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asm_entry!(r"^HALT$", |_, _| Ok(Instruction::Halt)), |
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asm_entry!(format!(r"^CLOAD\s{}$", REGEX_REG), parse_cload), |
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asm_entry!(format!(r"^ZERO\s{}$", REGEX_REG), parse_zero), |
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asm_entry!(r"^DIV$", |_, _| Ok(Instruction::Div)), |
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asm_entry!(r"^MUL$", |_, _| Ok(Instruction::Mul)), |
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asm_entry!(r"^SWAP$", |_, _| Ok(Instruction::Swap)), |
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asm_entry!(r"^PRTCHK$", |_, _| Ok(Instruction::PortReady)), |
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asm_entry!(r"^PRTRD$", |_, _| Ok(Instruction::ReadPort)), |
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asm_entry!(r"^PRTWR$", |_, _| Ok(Instruction::WritePort)), |
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], |
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} |
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} |
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pub fn assemble(&self, input: &str) -> Result<[u8; 0x100], Box<dyn Error>> { |
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let mut ret = [0u8; 0x100]; |
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let mut i: usize = 0; |
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for line in input.lines().map(|line| line.trim()) { |
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match line { |
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"" => (), |
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line => { |
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if i > 0xFF { |
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return Err("Too much instructions".into()); |
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} |
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let insn = self.line_to_insn(line)?; |
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ret[i] = encode(insn); |
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i += 1; |
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} |
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} |
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} |
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Ok(ret) |
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} |
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fn line_to_insn(&self, line: &str) -> Result<Instruction, Box<dyn Error>> { |
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for (regex, handler) in &self.table { |
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if regex.is_match(line) { |
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return handler(line, regex); |
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} |
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} |
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Err("Unknown instruction".into()) |
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} |
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} |
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fn parse_u128(src: &str) -> Result<u128, Box<dyn Error>> { |
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if let Some(s) = src.strip_prefix("0b") { |
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Ok(u128::from_str_radix(s, 2)?) |
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} else if let Some(s) = src.strip_prefix("0o") { |
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Ok(u128::from_str_radix(s, 8)?) |
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} else if let Some(s) = src.strip_prefix("0x") { |
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Ok(u128::from_str_radix(s, 16)?) |
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} else { |
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Ok(src.parse()?) |
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} |
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} |
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fn parse_u8(src: &str) -> Result<u8, Box<dyn Error>> { |
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match parse_u128(src)? { |
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x @ 0..=255 => Ok(x as u8), |
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x => Err(format!("{} is not in range [0, 255]", x).into()), |
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} |
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} |
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fn parse_i8(src: &str) -> Result<i8, Box<dyn Error>> { |
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let (sign, num): (i128, u128) = match src.strip_prefix('-') { |
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Some(s) => (-1, parse_u128(s)?), |
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None => (1, parse_u128(src)?), |
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}; |
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match (sign, num) { |
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(1, x) if x <= 127 => Ok((x as i128 * sign) as i8), |
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(-1, x) if x <= 128 => Ok((x as i128 * sign) as i8), |
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(_, x) => Err(format!("{} is not in range [-128, 127]", x).into()), |
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} |
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} |
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fn parse_u4(src: &str) -> Result<u4, Box<dyn Error>> { |
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match parse_u8(src)? { |
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x @ 0..=15 => Ok(u4::new(x)), |
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x => Err(format!("{} is not in range [0, 15]", x).into()), |
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} |
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} |
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fn parse_u3(src: &str) -> Result<u3, Box<dyn Error>> { |
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match parse_u8(src)? { |
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x @ 0..=7 => Ok(u3::new(x)), |
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x => Err(format!("{} is not in range [0, 7]", x).into()), |
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} |
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} |
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fn parse_reg(src: &str) -> Result<Register, Box<dyn Error>> { |
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match src { |
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"R0" => Ok(Register::R0), |
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"R1" => Ok(Register::R1), |
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x => Err(format!("'{}' is not a valid register", x).into()), |
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} |
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} |
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fn parse_reg_half(src: &str) -> Result<(Register, bool), Box<dyn Error>> { |
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match src { |
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"R0.l" => Ok((Register::R0, true)), |
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"R0.h" => Ok((Register::R0, false)), |
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"R1.l" => Ok((Register::R1, true)), |
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"R1.h" => Ok((Register::R1, false)), |
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x => Err(format!("'{}' is not a valid register half", x).into()), |
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} |
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} |
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fn parse_carry(src: &str) -> Result<bool, Box<dyn Error>> { |
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match src { |
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"0" => Ok(false), |
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"1" => Ok(true), |
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x => Err(format!("'{}' is an invalid carry value", x).into()), |
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} |
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} |
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fn parse_byte(line: &str, regex: &Regex) -> Result<Instruction, Box<dyn Error>> { |
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Ok(decode(parse_u8( |
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regex.captures(line).unwrap().get(1).unwrap().as_str(), |
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)?)) |
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} |
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fn parse_mov_reg_mem(line: &str, regex: &Regex) -> Result<Instruction, Box<dyn Error>> { |
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let captures = regex.captures(line).unwrap(); |
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let reg = parse_reg(captures.get(1).unwrap().as_str())?; |
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let addr = parse_u4(captures.get(2).unwrap().as_str())?; |
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Ok(Instruction::Load { reg, addr }) |
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} |
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fn parse_mov_mem_reg(line: &str, regex: &Regex) -> Result<Instruction, Box<dyn Error>> { |
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let captures = regex.captures(line).unwrap(); |
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let addr = parse_u4(captures.get(1).unwrap().as_str())?; |
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let reg = parse_reg(captures.get(2).unwrap().as_str())?; |
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Ok(Instruction::Store { reg, addr }) |
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} |
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fn parse_mov_reg_half_imm(line: &str, regex: &Regex) -> Result<Instruction, Box<dyn Error>> { |
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let captures = regex.captures(line).unwrap(); |
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let (reg, low) = parse_reg_half(captures.get(1).unwrap().as_str())?; |
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let val = parse_u4(captures.get(2).unwrap().as_str())?; |
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Ok(Instruction::LoadImmediate { low, reg, val }) |
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} |
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fn parse_mov_reg_reg(line: &str, regex: &Regex) -> Result<Instruction, Box<dyn Error>> { |
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let captures = regex.captures(line).unwrap(); |
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let reg_to = parse_reg(captures.get(1).unwrap().as_str())?; |
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let reg_from = parse_reg(captures.get(2).unwrap().as_str())?; |
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match (reg_to, reg_from) { |
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(Register::R0, Register::R1) => Ok(Instruction::Copy { |
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reg_from: Register::R1, |
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}), |
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(Register::R1, Register::R0) => Ok(Instruction::Copy { |
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reg_from: Register::R0, |
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}), |
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_ => Err("Malformed register to register copy".into()), |
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} |
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} |
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fn parse_jmp_impl( |
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line: &str, |
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regex: &Regex, |
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use_carry: bool, |
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) -> Result<Instruction, Box<dyn Error>> { |
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match parse_i8(regex.captures(line).unwrap().get(1).unwrap().as_str())? { |
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x @ -3..=-1 => Ok(Instruction::NearJumpBackward { |
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use_carry, |
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offset: u2::new(-x as u8), |
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}), |
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x @ 0..=7 => Ok(Instruction::NearJumpForward { |
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use_carry, |
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offset: u3::new(x as u8), |
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}), |
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x => Err(format!("{} is not a valid relative jump offset", x).into()), |
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} |
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} |
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fn parse_jmp(line: &str, regex: &Regex) -> Result<Instruction, Box<dyn Error>> { |
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parse_jmp_impl(line, regex, false) |
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} |
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fn parse_jmpc(line: &str, regex: &Regex) -> Result<Instruction, Box<dyn Error>> { |
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parse_jmp_impl(line, regex, true) |
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} |
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fn parse_ajmp_impl( |
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line: &str, |
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regex: &Regex, |
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use_carry: bool, |
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) -> Result<Instruction, Box<dyn Error>> { |
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let reg = parse_reg(regex.captures(line).unwrap().get(1).unwrap().as_str())?; |
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Ok(Instruction::FarJump { reg, use_carry }) |
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} |
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fn parse_ajmp(line: &str, regex: &Regex) -> Result<Instruction, Box<dyn Error>> { |
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parse_ajmp_impl(line, regex, false) |
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} |
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fn parse_ajmpc(line: &str, regex: &Regex) -> Result<Instruction, Box<dyn Error>> { |
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parse_ajmp_impl(line, regex, true) |
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} |
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fn parse_shift( |
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line: &str, |
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regex: &Regex, |
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right: bool, |
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mode: ShiftMode, |
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) -> Result<Instruction, Box<dyn Error>> { |
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let captures = regex.captures(line).unwrap(); |
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let reg = parse_reg(captures.get(1).unwrap().as_str())?; |
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let len = parse_u3(captures.get(2).unwrap().as_str())?; |
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Ok(Instruction::BitShift { |
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right, |
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reg, |
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mode, |
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len, |
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}) |
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} |
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fn parse_shr(line: &str, regex: &Regex) -> Result<Instruction, Box<dyn Error>> { |
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parse_shift(line, regex, true, ShiftMode::Logical) |
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} |
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fn parse_shl(line: &str, regex: &Regex) -> Result<Instruction, Box<dyn Error>> { |
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parse_shift(line, regex, false, ShiftMode::Logical) |
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} |
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fn parse_rotr(line: &str, regex: &Regex) -> Result<Instruction, Box<dyn Error>> { |
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parse_shift(line, regex, true, ShiftMode::Circular) |
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} |
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fn parse_rotl(line: &str, regex: &Regex) -> Result<Instruction, Box<dyn Error>> { |
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parse_shift(line, regex, false, ShiftMode::Circular) |
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} |
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fn parse_inc(line: &str, regex: &Regex) -> Result<Instruction, Box<dyn Error>> { |
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let reg = parse_reg(regex.captures(line).unwrap().get(1).unwrap().as_str())?; |
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Ok(Instruction::Inc { reg }) |
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} |
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fn parse_dec(line: &str, regex: &Regex) -> Result<Instruction, Box<dyn Error>> { |
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let reg = parse_reg(regex.captures(line).unwrap().get(1).unwrap().as_str())?; |
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Ok(Instruction::Dec { reg }) |
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} |
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fn parse_compl(line: &str, regex: &Regex) -> Result<Instruction, Box<dyn Error>> { |
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let reg = parse_reg(regex.captures(line).unwrap().get(1).unwrap().as_str())?; |
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Ok(Instruction::Complement { reg }) |
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} |
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fn parse_setc(line: &str, regex: &Regex) -> Result<Instruction, Box<dyn Error>> { |
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let carry = parse_carry(regex.captures(line).unwrap().get(1).unwrap().as_str())?; |
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Ok(Instruction::Setc { carry }) |
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} |
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fn parse_cload(line: &str, regex: &Regex) -> Result<Instruction, Box<dyn Error>> { |
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let reg = parse_reg(regex.captures(line).unwrap().get(1).unwrap().as_str())?; |
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Ok(Instruction::Cload { reg }) |
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} |
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fn parse_zero(line: &str, regex: &Regex) -> Result<Instruction, Box<dyn Error>> { |
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let reg = parse_reg(regex.captures(line).unwrap().get(1).unwrap().as_str())?; |
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Ok(Instruction::Zero { reg }) |
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} |
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#[cfg(test)] |
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mod tests { |
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use crate::assembler::Assembler; |
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use crate::instruction::{decode, Instruction, Register, ShiftMode}; |
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use lazy_static::lazy_static; |
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use std::fmt::{Binary, Display, LowerHex, Octal}; |
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use ux::{u2, u3, u4}; |
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lazy_static! { |
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static ref ASM: Assembler = Assembler::new(); |
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} |
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enum IntegerFormat { |
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Decimal, |
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Binary, |
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Octal, |
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Hexadecimal, |
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None, |
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} |
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struct PrintIntegers<T: Display + Binary + Octal + LowerHex> { |
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num: T, |
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format: IntegerFormat, |
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} |
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impl<T: Display + Binary + Octal + LowerHex> PrintIntegers<T> { |
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fn new(num: T) -> Self { |
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PrintIntegers { |
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num, |
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format: IntegerFormat::Decimal, |
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} |
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} |
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} |
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impl<T: Display + Binary + Octal + LowerHex> Iterator for PrintIntegers<T> { |
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type Item = String; |
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fn next(&mut self) -> Option<Self::Item> { |
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match self.format { |
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IntegerFormat::Decimal => { |
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self.format = IntegerFormat::Binary; |
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Some(format!("{}", self.num)) |
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} |
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IntegerFormat::Binary => { |
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self.format = IntegerFormat::Octal; |
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Some(format!("{:#b}", self.num)) |
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} |
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IntegerFormat::Octal => { |
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self.format = IntegerFormat::Hexadecimal; |
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Some(format!("{:#o}", self.num)) |
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} |
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IntegerFormat::Hexadecimal => { |
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self.format = IntegerFormat::None; |
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Some(format!("{:#x}", self.num)) |
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} |
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IntegerFormat::None => None, |
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} |
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} |
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} |
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macro_rules! make_test_insn_no_args { |
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($name:ident, $line:expr, $insn:expr) => { |
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#[test] |
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fn $name() { |
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assert_eq!(ASM.line_to_insn($line).unwrap(), $insn); |
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} |
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}; |
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} |
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make_test_insn_no_args!(asm_line_eq, "EQ", Instruction::CmpEqual); |
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make_test_insn_no_args!(asm_line_gt, "GT", Instruction::CmpGreater); |
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make_test_insn_no_args!(asm_line_le, "LE", Instruction::CmpLess); |
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make_test_insn_no_args!(asm_line_not, "NOT", Instruction::Not); |
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make_test_insn_no_args!(asm_line_add, "ADD", Instruction::Add); |
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make_test_insn_no_args!(asm_line_sub, "SUB", Instruction::Sub); |
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make_test_insn_no_args!(asm_line_and, "AND", Instruction::And); |
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make_test_insn_no_args!(asm_line_or, "OR", Instruction::Or); |
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make_test_insn_no_args!(asm_line_xor, "XOR", Instruction::Xor); |
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make_test_insn_no_args!(asm_line_xnor, "XNOR", Instruction::Xnor); |
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make_test_insn_no_args!(asm_line_nop, "NOP", Instruction::Nop); |
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make_test_insn_no_args!(asm_line_halt, "HALT", Instruction::Halt); |
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make_test_insn_no_args!(asm_line_div, "DIV", Instruction::Div); |
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make_test_insn_no_args!(asm_line_mul, "MUL", Instruction::Mul); |
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make_test_insn_no_args!(asm_line_swap, "SWAP", Instruction::Swap); |
|||
make_test_insn_no_args!(asm_line_prtchk, "PRTCHK", Instruction::PortReady); |
|||
make_test_insn_no_args!(asm_line_prtrd, "PRTRD", Instruction::ReadPort); |
|||
make_test_insn_no_args!(asm_line_prtwr, "PRTWR", Instruction::WritePort); |
|||
make_test_insn_no_args!( |
|||
asm_line_shr, |
|||
"SHR", |
|||
Instruction::BitShiftVar { |
|||
mode: ShiftMode::Logical, |
|||
right: true |
|||
} |
|||
); |
|||
make_test_insn_no_args!( |
|||
asm_line_shl, |
|||
"SHL", |
|||
Instruction::BitShiftVar { |
|||
mode: ShiftMode::Logical, |
|||
right: false |
|||
} |
|||
); |
|||
make_test_insn_no_args!( |
|||
asm_line_rotr, |
|||
"ROTR", |
|||
Instruction::BitShiftVar { |
|||
mode: ShiftMode::Circular, |
|||
right: true |
|||
} |
|||
); |
|||
make_test_insn_no_args!( |
|||
asm_line_rotl, |
|||
"ROTL", |
|||
Instruction::BitShiftVar { |
|||
mode: ShiftMode::Circular, |
|||
right: false |
|||
} |
|||
); |
|||
|
|||
#[test] |
|||
fn asm_line_byte() { |
|||
for i in 0..=255u8 { |
|||
for j in PrintIntegers::new(i) { |
|||
assert_eq!(ASM.line_to_insn(&format!("BYTE {}", j)).unwrap(), decode(i)); |
|||
} |
|||
} |
|||
} |
|||
|
|||
#[test] |
|||
fn asm_line_mov_reg_mem() { |
|||
for (reg_str, reg) in [("R0", Register::R0)] { |
|||
for i in 0..=15u8 { |
|||
for j in PrintIntegers::new(i) { |
|||
assert_eq!( |
|||
ASM.line_to_insn(&format!("MOV {}, [{}]", reg_str, j)) |
|||
.unwrap(), |
|||
Instruction::Load { |
|||
reg: reg.clone(), |
|||
addr: u4::new(i) |
|||
} |
|||
); |
|||
} |
|||
} |
|||
} |
|||
} |
|||
|
|||
#[test] |
|||
fn asm_line_mov_mem_reg() { |
|||
for (reg_str, reg) in [("R0", Register::R0)] { |
|||
for i in 0..=15u8 { |
|||
for j in PrintIntegers::new(i) { |
|||
assert_eq!( |
|||
ASM.line_to_insn(&format!("MOV [{}], {}", j, reg_str)) |
|||
.unwrap(), |
|||
Instruction::Store { |
|||
reg: reg.clone(), |
|||
addr: u4::new(i) |
|||
} |
|||
); |
|||
} |
|||
} |
|||
} |
|||
} |
|||
|
|||
#[test] |
|||
fn asm_line_mov_reg_half_imm() { |
|||
for (reg_str, reg) in [("R0", Register::R0), ("R1", Register::R1)] { |
|||
for (low_str, low) in [("l", true), ("h", false)] { |
|||
for i in 0..=15 { |
|||
for j in PrintIntegers::new(i) { |
|||
assert_eq!( |
|||
ASM.line_to_insn(&format!("MOV {}.{}, {}", reg_str, low_str, j)) |
|||
.unwrap(), |
|||
Instruction::LoadImmediate { |
|||
low, |
|||
reg: reg.clone(), |
|||
val: u4::new(i) |
|||
} |
|||
); |
|||
} |
|||
} |
|||
} |
|||
} |
|||
} |
|||
|
|||
#[test] |
|||
fn asm_line_jmp() { |
|||
for i in 0..=7u8 { |
|||
for j in PrintIntegers::new(i) { |
|||
assert_eq!( |
|||
ASM.line_to_insn(&format!("JMP {}", j)).unwrap(), |
|||
Instruction::NearJumpForward { |
|||
use_carry: false, |
|||
offset: u3::new(i) |
|||
} |
|||
) |
|||
} |
|||
} |
|||
for i in 1..=3u8 { |
|||
for j in PrintIntegers::new(i) { |
|||
assert_eq!( |
|||
ASM.line_to_insn(&format!("JMP -{}", j)).unwrap(), |
|||
Instruction::NearJumpBackward { |
|||
use_carry: false, |
|||
offset: u2::new(i) |
|||
} |
|||
) |
|||
} |
|||
} |
|||
} |
|||
|
|||
#[test] |
|||
fn asm_line_jmpc() { |
|||
for i in 0..=7u8 { |
|||
for j in PrintIntegers::new(i) { |
|||
assert_eq!( |
|||
ASM.line_to_insn(&format!("JMPC {}", j)).unwrap(), |
|||
Instruction::NearJumpForward { |
|||
use_carry: true, |
|||
offset: u3::new(i) |
|||
} |
|||
) |
|||
} |
|||
} |
|||
for i in 1..=3u8 { |
|||
for j in PrintIntegers::new(i) { |
|||
assert_eq!( |
|||
ASM.line_to_insn(&format!("JMPC -{}", j)).unwrap(), |
|||
Instruction::NearJumpBackward { |
|||
use_carry: true, |
|||
offset: u2::new(i) |
|||
} |
|||
) |
|||
} |
|||
} |
|||
} |
|||
|
|||
#[test] |
|||
fn asm_lime_ajmp() { |
|||
assert_eq!( |
|||
ASM.line_to_insn("AJMP R0").unwrap(), |
|||
Instruction::FarJump { |
|||
reg: Register::R0, |
|||
use_carry: false |
|||
} |
|||
); |
|||
assert_eq!( |
|||
ASM.line_to_insn("AJMP R1").unwrap(), |
|||
Instruction::FarJump { |
|||
reg: Register::R1, |
|||
use_carry: false |
|||
} |
|||
); |
|||
} |
|||
|
|||
#[test] |
|||
fn asm_lime_ajmpc() { |
|||
for (reg_str, reg) in [("R0", Register::R0), ("R1", Register::R1)] { |
|||
assert_eq!( |
|||
ASM.line_to_insn(&format!("AJMPC {}", reg_str)).unwrap(), |
|||
Instruction::FarJump { |
|||
reg, |
|||
use_carry: true |
|||
} |
|||
); |
|||
} |
|||
} |
|||
|
|||
#[test] |
|||
fn asm_line_shift_rotate() { |
|||
for (insn, right, mode) in [ |
|||
("SHR", true, ShiftMode::Logical), |
|||
("SHL", false, ShiftMode::Logical), |
|||
("ROTR", true, ShiftMode::Circular), |
|||
("ROTL", false, ShiftMode::Circular), |
|||
] { |
|||
for (reg_str, reg) in [("R0", Register::R0), ("R1", Register::R1)] { |
|||
for i in 0..7u8 { |
|||
for j in PrintIntegers::new(i) { |
|||
assert_eq!( |
|||
ASM.line_to_insn(&format!("{} {}, {}", insn, reg_str, j)) |
|||
.unwrap(), |
|||
Instruction::BitShift { |
|||
right, |
|||
reg: reg.clone(), |
|||
mode: mode.clone(), |
|||
len: u3::new(i) |
|||
} |
|||
) |
|||
} |
|||
} |
|||
} |
|||
} |
|||
} |
|||
|
|||
#[test] |
|||
fn asm_line_inc() { |
|||
for (reg_str, reg) in [("R0", Register::R0), ("R1", Register::R1)] { |
|||
assert_eq!( |
|||
ASM.line_to_insn(&format!("INC {}", reg_str)).unwrap(), |
|||
Instruction::Inc { reg } |
|||
); |
|||
} |
|||
} |
|||
|
|||
#[test] |
|||
fn asm_line_dec() { |
|||
for (reg_str, reg) in [("R0", Register::R0), ("R1", Register::R1)] { |
|||
assert_eq!( |
|||
ASM.line_to_insn(&format!("DEC {}", reg_str)).unwrap(), |
|||
Instruction::Dec { reg } |
|||
); |
|||
} |
|||
} |
|||
|
|||
#[test] |
|||
fn asm_line_compl() { |
|||
for (reg_str, reg) in [("R0", Register::R0), ("R1", Register::R1)] { |
|||
assert_eq!( |
|||
ASM.line_to_insn(&format!("COMPL {}", reg_str)).unwrap(), |
|||
Instruction::Complement { reg } |
|||
); |
|||
} |
|||
} |
|||
|
|||
#[test] |
|||
fn asm_line_setc() { |
|||
for (i, carry) in [(0, false), (1, true)] { |
|||
assert_eq!( |
|||
ASM.line_to_insn(&format!("SETC {}", i)).unwrap(), |
|||
Instruction::Setc { carry } |
|||
) |
|||
} |
|||
} |
|||
|
|||
#[test] |
|||
fn asm_line_cload() { |
|||
for (reg_str, reg) in [("R0", Register::R0), ("R1", Register::R1)] { |
|||
assert_eq!( |
|||
ASM.line_to_insn(&format!("CLOAD {}", reg_str)).unwrap(), |
|||
Instruction::Cload { reg } |
|||
); |
|||
} |
|||
} |
|||
|
|||
#[test] |
|||
fn asm_line_zero() { |
|||
for (reg_str, reg) in [("R0", Register::R0), ("R1", Register::R1)] { |
|||
assert_eq!( |
|||
ASM.line_to_insn(&format!("ZERO {}", reg_str)).unwrap(), |
|||
Instruction::Zero { reg } |
|||
); |
|||
} |
|||
} |
|||
} |
|||
Loading…
Reference in new issue