diff --git a/DESIGN.md b/DESIGN.md
index ee8b775..d7cd0d8 100644
--- a/DESIGN.md
+++ b/DESIGN.md
@@ -134,7 +134,7 @@ write `0` otherwise.
 Flips value in `C`. Use it to implement 'not equal', 'greater or equal',
 and 'less or equal' comparisons.
 
-### BIT SHIFT
+### BIT SHIFT RIGHT
 
 ```
 +—+—+—+—+—+—————+
@@ -146,11 +146,27 @@ and 'less or equal' comparisons.
 
 `M` — mode of operation, `0` — logical shift, `1` — circular shift.
 
+`L` — length of shift.
+
+### BIT SHIFT LEFT
+
+```
++—+—+—+—+—+—————+
+|1|1|0|R|M|L L L|
++—+—+—+—+—+—————+
+```
+
+`R` — `0` to shift bits in `R0` register, `1` in `R1` register.
+
+`M` — mode of operation, `0` — logical shift, `1` — circular shift.
+
+`L` — length of shift.
+
 ### INCREMENT
 
 ```
 +—+—+—+—+—+—+—+—+
-|1|1|0|0|0|0|0|R|
+|1|1|1|0|0|0|0|R|
 +—+—+—+—+—+—+—+—+
 ```
 
@@ -162,7 +178,7 @@ Increments ALU register and sets `C` if result is zero.
 
 ```
 +—+—+—+—+—+—+—+—+
-|1|1|0|0|0|0|1|R|
+|1|1|1|0|0|0|1|R|
 +—+—+—+—+—+—+—+—+
 ```
 
@@ -174,7 +190,7 @@ Decrements ALU register and sets `C` if result is zero.
 
 ```
 +—+—+—+—+—+—+—+—+
-|1|1|0|0|0|1|0|0|
+|1|1|1|0|0|1|0|0|
 +—+—+—+—+—+—+—+—+
 ```
 
@@ -185,7 +201,7 @@ Sets `C` if result overflows.
 
 ```
 +—+—+—+—+—+—+—+—+
-|1|1|0|0|0|1|0|1|
+|1|1|1|0|0|1|0|1|
 +—+—+—+—+—+—+—+—+
 ```
 
@@ -196,7 +212,7 @@ Sets `C` if result underflows.
 
 ```
 +—+—+—+—+—+—+—+—+
-|1|1|0|0|0|1|1|0|
+|1|1|1|0|0|1|1|0|
 +—+—+—+—+—+—+—+—+
 ```
 
@@ -207,7 +223,7 @@ and storing result in `R0`.
 
 ```
 +—+—+—+—+—+—+—+—+
-|1|1|0|0|0|1|1|1|
+|1|1|1|0|0|1|1|1|
 +—+—+—+—+—+—+—+—+
 ```
 
@@ -218,7 +234,7 @@ and storing result in `R0`.
 
 ```
 +—+—+—+—+—+—+—+—+
-|1|1|0|0|1|0|0|0|
+|1|1|1|0|1|0|0|0|
 +—+—+—+—+—+—+—+—+
 ```
 
@@ -229,7 +245,7 @@ and storing result in `R0`.
 
 ```
 +—+—+—+—+—+—+—+—+
-|1|1|0|0|1|0|0|1|
+|1|1|1|0|1|0|0|1|
 +—+—+—+—+—+—+—+—+
 ```
 
@@ -240,10 +256,152 @@ and storing result in `R0`.
 
 ```
 +—+—+—+—+—+—+—+—+
-|1|1|0|0|1|0|1|R|
+|1|1|1|0|1|0|1|R|
 +—+—+—+—+—+—+—+—+
 ```
 
 Flip all bits in ALU register.
 
 `R` — `0` to use `R0`, `1` to use `R1`.
+
+### VARIABLE BIT SHIFT
+
+```
++—+—+—+—+—+—+—+—+
+|1|1|1|0|1|1|D|M|
++—+—+—+—+—+—+—+—+
+```
+
+Shifts value in `R0` by length specified in `R1` and stores result in `R0`.
+If `R1` value is greater than 8, `R0` is zeroed.
+`C` is set if `R0` is zeroed.
+
+`D` — direction: `0` to shift bits right, `1` — left.
+
+`M` — mode of operation, `0` — logical shift, `1` — circular shift.
+
+### COPY
+
+```
++—+—+—+—+—+—+—+—+
+|1|1|1|1|0|0|0|R|
++—+—+—+—+—+—+—+—+
+```
+
+`R` — `0` to copy data from `R0` to `R1`, `1` to copy data from `R1` to `R0`.
+
+### SETC
+
+```
++—+—+—+—+—+—+—+—+
+|1|1|1|1|0|0|1|C|
++—+—+—+—+—+—+—+—+
+```
+
+`C` — value copied to `C` flag.
+
+### NOP
+
+```
++—+—+—+—+—+—+—+—+
+|1|1|1|1|0|1|0|0|
++—+—+—+—+—+—+—+—+
+```
+
+### HALT
+
+```
++—+—+—+—+—+—+—+—+
+|1|1|1|1|0|1|0|1|
++—+—+—+—+—+—+—+—+
+```
+
+Resets CPU registers and memory and zeroes `IP`.
+
+### CLOAD
+
+```
++—+—+—+—+—+—+—+—+
+|1|1|1|1|0|1|1|R|
++—+—+—+—+—+—+—+—+
+```
+
+Loads byte from `CODE` segment at address specified in `R0`
+and puts it into ALU register.
+
+`R` — `0` to store result in `R0`, `1` to store result in `R1`.
+
+### ZERO
+
+```
++—+—+—+—+—+—+—+—+
+|1|1|1|1|1|0|0|R|
++—+—+—+—+—+—+—+—+
+```
+
+`R` — `0` to zero out `R0`, `1` to zero out `R1`.
+
+### DIV
+
+```
++—+—+—+—+—+—+—+—+
+|1|1|1|1|1|0|1|0|
++—+—+—+—+—+—+—+—+
+```
+
+Divides `R0` by `R1`. Stores quotient in `R0` and remainder in `R1`.
+If `R1` is 0 before division, sets `R0` to all ones and `R1` to all zeroes,
+also sets `C` flag.
+
+### MUL
+
+```
++—+—+—+—+—+—+—+—+
+|1|1|1|1|1|0|1|1|
++—+—+—+—+—+—+—+—+
+```
+
+Multiplies `R0` by `R1`. Result is unsigned 16-bit value. Most significant
+byte is stored in `R0` and least significant byte is stored in `R1`.
+
+### SWAP
+
+```
++—+—+—+—+—+—+—+—+
+|1|1|1|1|1|1|0|0|
++—+—+—+—+—+—+—+—+
+```
+
+Swaps values of `R0` and `R1`.
+
+### PORT READY
+
+```
++—+—+—+—+—+—+—+—+
+|1|1|1|1|1|1|0|1|
++—+—+—+—+—+—+—+—+
+```
+
+If there is data available to read from port, sets `C` flag.
+Otherwise, unsets `C` flag.
+
+### READ PORT
+
+```
++—+—+—+—+—+—+—+—+
+|1|1|1|1|1|1|1|0|
++—+—+—+—+—+—+—+—+
+```
+
+Reads byte from port and stores result in `R0`. If there is no
+data available from port, zeroes out `R0`.
+
+### WRITE PORT
+
+```
++—+—+—+—+—+—+—+—+
+|1|1|1|1|1|1|1|1|
++—+—+—+—+—+—+—+—+
+```
+
+Writes byte from `R0` to port.